The present invention relates to semiconductor memory devices and, more particularly to a technique effective for relieving defects of a dynamic RAM (random access memory) of an increased storage capacity, for example.
In a defect relieving technique for semiconductor memory devices, a row or column (a word line or data line) including a defective bit is collectively replaced by a stand-by row or column (a stand-by word line or a stand-by data line). While such a defect relieving technique is effective when breaking of wire or short-circuit fault has occurred, it degrades the efficiency for random defects caused by silicon crystals. There is known a semiconductor memory device such as disclosed in JP-A-1-303699, having a defect relieving circuit in which a defective bit, specified as an intersection of a row and a column is replaced by a redundant bit prepared in a stand-by row or column in one-to-one correspondence.
The above described defect relieving circuit disclosed in JP-A-1-303699, can relieve random defects efficiently in a memory device having an extremely small storage capacity. However, it is not suitable to memory devices having large storage capacities, such as approximately 16 Mbits or 64 Mbits, which are now being developed. This is because outputs of a row decoder and a column decoder are supplied to a comparator circuit in order to detect a defective bit and are compared with the output of a ROM storing therein a defective address beforehand. Assuming now that the memory device has a storage capacity of 16 Mbits, for example, each of the row and column simply has 4096 decode outputs. In order to specify one defective cell in the ROM, 4096 fuses are required for each of the row and column. Since the comparator circuit makes as many signal comparisons as 8192 bits in total, it has an extremely large circuit scale. In this way, 8192 fuses, 8192 signal buses, and a comparator circuit making as many comparisons as 8192 bits are required for relieving only one defect bit.
In a dynamic RAM such as the above described dynamic RAM having 16 Mbits, the operation speed is lowered because of an increase in the number of memory cells connected to the word line and data line and power dissipation must thus be decreased. Therefore, the word line and data line are divided, and the RAM is formed by a plurality of memory mats, memory arrays, or memory blocks. Depending upon such division of the word line, the number of apparent decode outputs increases. In the above described defect relieving method, therefore, the number of fuses included in the ROM and the number of actual bits compared by the comparator circuit increase, resulting in a further increase of the circuit scale.
In order to decrease the circuit scale of the defect relieving method disclosed in the above described JP-A-1-303699, the present inventors thought of comparing address signals instead of decode outputs as described in JP-A-1-303699. This is because only 24 bits of information suffice in the case of comparing address signals even in dynamic RAMs having a large memory capacity, such as 16-Mbit dynamic RAMs. For specifying one defect cell, however, a ROM having 24 fuses and a comparator circuit for comparing the output signal of this ROM with the above described address signal having 24 bits is still needed. For relieving random defects as described above, relieving several bits or so is, for all practical purposes meaningless. Actually, a capability of relieving at least 100 bits or so is needed. Even if a comparison method using address signals as described above is adopted, however, an extremely large number of fuses and a comparator circuit having an extremely large circuit scale would still be needed.